Digital buffer circuit
US10707872B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2019 |
| Grant date | Jul 7, 2020 |
| Priority date | — |
| Expiry date | Jul 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Circuits and techniques for buffering a digital signal are disclosed. The circuits and techniques allow a digital buffer circuit to accommodate a range of output voltages while maintaining a delay between input and output that is suitable for digital communications. The disclosed circuits and techniques utilize a combination of low voltage switches and high voltage switches. The low voltage switches dominate the buffering process when the buffer drives external circuitry (e.g., a communications bus) having a low voltage then, and the high voltage switches dominate the buffering process when the buffer drives external circuitry having a high voltage. The high voltage and low voltage switches configure themselves automatically based on an operating condition determined by the voltage level of the output with respect to the voltage level of the input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.