Method and apparatus for efficient binary and ternary support in fused multiply-add (FMA) circuits
US10713012B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Jan 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying a multiply-accumulate or multiply-add operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range; control circuitry, responsive to a precision of the first and second operands being below a threshold, to cause the first operand and second operand to be processed by the second multiplication circuitry to generate the result; and adder circuitry to add the result to an accumulated value to generate a new accumulated value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.