Bit shuffle processors, methods, systems, and instructions
US10713044B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2015 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes packed data registers and a decode unit to decode an instruction. The instruction is to indicate a first source operand having at least one lane of bits, and a second source packed data operand having a number of sub-lane sized bit selection elements. An execution unit is coupled with the packed data registers and the decode unit. The execution unit, in response to the instruction, stores a result operand in a destination storage location. The result operand includes, a different corresponding bit for each of the number of sub-lane sized bit selection elements. A value of each bit of the result operand corresponding to a sub-lane sized bit selection element is that of a bit of a corresponding lane of bits, of the at least one lane of bits of the first source operand, which is indicated by the corresponding sub-lane sized bit selection element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.