Multi-core processor and method of controlling the same using revisable translation tables
US10713095B2 · kind B2 · utility
18Cited by
10References
17Claims
0Family size
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Key dates
| Filing date | Mar 27, 2017 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 30, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of controlling a multi-core processor includes allocating at least one core of the multi-core processor to at least one process for execution; generating a translation table with respect to the at least one process to translate a logical ID of the at least one core allocated to the at least one process to a physical ID; and controlling the at least one process based on the translation table generated with respect to the at least one process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.