Bernhard Egger
31Patents
3h-index
34Co-inventors
59Inventor score
Filing activity: Sep 21, 2009 → Nov 1, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10713095B2 | Multi-core processor and method of controlling the same using revisable translation tables | Emerging Cross-Sectional Technologies | 18 | Active |
| US9164769B2 | Analyzing data flow graph to detect data for copying from central register file to local register file used in different execution modes in reconfigurable processing array | Physics | 4 | Active |
| US8555005B2 | Memory managing apparatus and method using a pointer indicator bit to perform garbage collection | Physics | 3 | Active |
| US8745608B2 | Scheduler of reconfigurable array, method of scheduling commands, and computing apparatus | Physics | 3 | Active |
| US8601244B2 | Apparatus and method for generating VLIW, and processor and method for processing VLIW | Physics | 3 | Active |
| US8930672B2 | Multiprocessor using a shared virtual memory and method of generating a translation table | Emerging Cross-Sectional Technologies | 2 | Active |
| US8869129B2 | Apparatus and method for scheduling instruction | Physics | 2 | Active |
| US8495345B2 | Computing apparatus and method of handling interrupt | Physics | 1 | Active |
| US9959191B2 | Dynamic library profiling method and dynamic library profiling system | Physics | 1 | Active |
| US9411582B2 | Apparatus and method for processing invalid operation in prologue or epilogue of loop | Physics | 1 | Active |
| US8856596B2 | Debugging apparatus and method | Physics | 1 | Active |
| US8984475B2 | Apparatus and method for generating code overlay | Physics | 1 | Active |
| US9063735B2 | Reconfigurable processor and method for processing loop having memory dependency | Physics | 1 | Active |
| US8930929B2 | Reconfigurable processor and method for processing a nested loop | Physics | 1 | Active |
| US9304967B2 | Reconfigurable processor using power gating, compiler and compiling method thereof | Emerging Cross-Sectional Technologies | 0 | Active |
| US12321733B2 | Apparatus and method with neural network computation scheduling | Physics | 0 | Active |
| US10140247B2 | Electronic device, reconfigurable processor and controlling methods thereof | Emerging Cross-Sectional Technologies | 0 | Active |
| US10409351B2 | Computing devices and methods of allocating power to plurality of cores in each computing device | Emerging Cross-Sectional Technologies | 0 | Active |
| US8850170B2 | Apparatus and method for dynamically determining execution mode of reconfigurable array | Physics | 0 | Active |
| US8417918B2 | Reconfigurable processor with designated processing elements and reserved portion of register file for interrupt processing | Physics | 0 | Active |
| US9727528B2 | Reconfigurable processor with routing node frequency based on the number of routing nodes | Physics | 0 | Active |
| US9141498B2 | Method for verification of reconfigurable processor | Physics | 0 | Active |
| US8677099B2 | Reconfigurable processor with predicate signal activated operation configuration memory and separate routing configuration memory | Emerging Cross-Sectional Technologies | 0 | Active |
| US8516231B2 | Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus | Physics | 0 | Active |
| US9286074B2 | NOP instruction compressing apparatus and method in a VLIW machine | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.