Apparatuses and method for trimming input buffers based on identified mismatches
US10714156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45475
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.