Semiconductor device having hydrogen in a dielectric layer
US10714348B2 · kind B2 · utility
3Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Sep 12, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Sep 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.