MOS transistor with reduced hump effect
US10714583B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Jul 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A MOS transistor is produced on and in an active zone which includes a source region and a drain region. The active zone is surrounded by an insulating region. A conductive gate region of the transistor has two flanks which extend transversely to a source-drain direction, and the conductive gate region overlaps two opposite edges of the active zone act overlap zones. The conductive gate region includes, at a location of at least one overlap zone, at least one conductive tag which projects from at least one flank at a foot of the conductive gate region. The conductive tag covers a part of the active zone and a part of the insulating region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.