Large height tree-like sub 30nm vias to reduce conductive material re-deposition for sub 60nm MRAM devices
US10714680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Aug 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A stack of connecting metal vias is formed on a bottom electrode by repeating steps of depositing a conductive via layer, patterning and trimming the conductive via layer to form a sub 30 nm conductive via, encapsulating the conductive via with a dielectric layer, and exposing a top surface of the conductive via. A MTJ stack is deposited on the encapsulated via stack. A top electrode layer is deposited on the MTJ stack and patterned and trimmed to form a sub 60 nm hard mask. The MTJ stack is etched using the hard mask to form an MTJ device and over etched into the encapsulation layers but not into the bottom electrode wherein metal re-deposition material is formed on sidewalls of the encapsulation layers underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.