Flip-flop with single pre-charge node
US10715118B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.