Apparatus and methods for digital phase locked loop with analog proportional control function
US10715155B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Oct 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described herein is a digital phase locked loop (PLL) which includes a phase frequency detector (PFD) outputting a pulse width modulated (PWM) up pulse and a PWM down pulse based on comparison of a reference clock and a feedback clock, a digital integral circuit connected to the PFD, the digital integral circuit outputting a digital control signal based on the PWM up and down pulses, and a controlled oscillator (CO) connected to the digital integral circuit and an output and input of the PFD. The CO receiving the PWM up and down pulses from the PFD and adjusting a frequency of the CO based on the digital control signal and the PWM up and down pulses to generate an output clock. The feedback clock is based on the output clock and the reference clock is aligned with the feedback clock by adjusting the output clock frequency until frequency/phase lock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.