Analog-to-digital converter with adjustable operation frequency for noise reduction
US10715172B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2019 |
| Grant date | Jul 14, 2020 |
| Priority date | — |
| Expiry date | Jul 2, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/498
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an analog-to-digital converter with an adjustable operation frequency for noise reduction. The operation frequency of the analog-to-digital converter is adjustable, and if an input signal or a circuit is affected by a noise, the noise can be reduced by spreading the frequency distribution of the noise. A clock generator generates a clock signal for controlling the operation frequency of the analog-to-digital converter. Additionally, a clock controller receives a setting signal and a counting signal, controls the clock generator, and adjusts the frequency of the clock signal. In addition, a counter counts the number of periods of the clock signal, and generates the counting signal. Furthermore, a selecting signal makes the frequency of the clock signal gradually increase or decrease with time, thereby allowing change rate or change amount of the frequency of the clock signal to be adjustable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.