Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
US10719434B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 14, 2014 |
| Grant date | Jul 21, 2020 |
| Priority date | — |
| Expiry date | Dec 8, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache stores 2{circumflex over ( )}J-byte cache lines has an array of 2{circumflex over ( )}N sets each holds tags each X bits and 2{circumflex over ( )}W ways. An input receives a Q-bit address, MA[(Q−1):0], having a tag MA[(Q−1):(Q−X)] and index MA[(Q−X−1):J]. Q is at least (N+J+X−1). Set selection logic selects one set using the index and tag LSB; comparison logic compares all but the LSB of the tag with all but the LSB of each tag in the selected set and indicates a hit if a match; allocation logic, when the comparison logic indicates there is not a match: allocates into any of the 2{circumflex over ( )}W ways of the selected set when operating in a first mode; and into a subset of the 2{circumflex over ( )}W ways of the selected set when operating in a second mode. The subset of is limited based on bits of the tag portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.