Tunneling field effect transistor 3D NAND data cell structure and method for forming the same

US10720442B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Xin Huang · Beijing, CN
• Qi Wang · Singapore, SG
• Xiang Fu · San Diego, US
• Zhiliang Xia · 红钢城街道, CN
• Huang Peng Zhang · Zhejiang, CN
• Hua CAO · Hubei, CN

Key dates

• Filing date: Jul 26, 2018
• Grant date: Jul 21, 2020
• Expiry date: Jul 26, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a plurality vertical memory strings disposed through an alternating conductor/dielectric stack. Each of the memory strings includes a composite dielectric layers and a TFET semiconductor layer. The TFET semiconductor layer includes an n-type semiconductor layer and a p-type semiconductor layer.