Method for calibrating the read latency of a DDR DRAM module
US10725681B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2016 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jul 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for automatic calibration of read latency of a memory module is envisaged. The read latency is initially set to a default maximum value. The default maximum value is equivalent to the number of clock cycles required to complete a data read operation. A data pattern to be read from the memory module in consideration of the default maximum value is identified. A memory read operation is preformed, and a first data pattern is captured, in accordance with the default maximum value. The identified data pattern is compared with the first data pattern, and the default maximum value is iteratively calibrated based on the comparison thereof. Aforementioned steps are repeated across a plurality of memory read operations, and variations ire the maximum default value are tracked, and an average maximum value is calculated based thereupon. The average maximum value is assigned as the read latency for the memory module.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.