Method and apparatus for error detection and correction
US10725841B1 · kind B1 · utility
12Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2017 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Apr 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.