Patent · US Active

Processor with selective data storage (of accelerator) operable as either victim cache data storage or accelerator memory and having victim cache tags in lower level cache wherein evicted cache line is stored in said data storage when said data storage is in a first mode and said cache line is stored in system memory rather then said data store when said data storage is in a second mode

US10725934B2 · kind B2 · utility

2Cited by

5References

20Claims

0Family size

Assignee

SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD. · CN

Inventors

G. Glenn Henry · Austin, US
Terry Parks · Austin, US
Douglas R. Reed · Austin, US

Key dates

Filing date	May 16, 2018
Grant date	Jul 28, 2020
Priority date	—
Expiry date	Apr 11, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/27
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A first data storage holds cache lines, an accelerator has a second data storage that selectively holds accelerator data and cache lines evicted from the first data storage, a tag directory holds tags for cache lines stored in the first and second data storages, and a mode indicator indicates whether the second data storage is operating in a first or second mode in which it respectively holds cache lines evicted from the first data storage or accelerator data. In response to a request to evict a cache line from the first data storage, in the first mode the control logic writes the cache line to the second data storage and updates a tag in the tag directory to indicate the cache line is present in the second data storage, and in the second mode the control logic instead writes the cache line to a system memory.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.