Low-power data transfer from buffer to flash memory
US10726879B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Dec 8, 2017 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Dec 8, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A solid-state drive (SSD) may include a volatile buffer such as DRAM, a non-volatile memory (NVM) such as NAND Flash connected to the volatile buffer, and a capacitor connected to both, where the capacitor may have an energy capacity insufficient to supply the buffer and NVM using a normal supply voltage in a normal mode, but sufficient to supply the buffer and NVM using at least one reduced supply voltage in a temporary mode; and a related method may include programming data to the NVM by temporarily reducing the supply voltage to the NVM, and writing data to the NVM using the reduced supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.