Memory circuits precharging memory cell arrays and memory devices including the same
US10726886B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit and a memory device including the same are provided. The memory circuit may be connected to a bit line and a complementary bit line and configured to perform precharging on the bit line and the complementary bit line. The memory circuit may include: an equalizer configured to equalize voltage levels of the bit line and the complementary bit line by connecting the bit line with the complementary bit line in response to an equalizing signal; and a precharger configured to precharge the bit line and the complementary bit line to a precharge voltage in response to a precharge signal. The equalizing signal and the precharge signal may be received via separate lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.