Soo-Bong Chang
15Patents
4h-index
20Co-inventors
60Inventor score
Filing activity: Mar 9, 2000 → Jan 27, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6327190A | Complementary differential input buffer for a semiconductor memory device | Physics | 5 | Expired |
| US8009494B2 | Semiconductor memory device implementing full-VDD bit line precharge scheme using bit line sense amplifier | Physics | 5 | Active |
| US7660141B2 | Layout structures and methods of fabricating layout structures | Electricity | 5 | Active |
| US6847536B1 | Semiconductor memory device having structure for preventing level of boosting voltage applied to a node from dropping and method of forming the same | Electricity | 4 | Expired |
| US10726886B2 | Memory circuits precharging memory cell arrays and memory devices including the same | Physics | 3 | Active |
| US7474549B2 | Bit-line equalizer, semiconductor memory device including the same, and method for manufacturing bit-line equalizer | Electricity | 3 | Active |
| US7359280B2 | Layout structure for sub word line drivers and method thereof | Electricity | 3 | Active |
| US7864599B2 | Device and method generating internal voltage in semiconductor memory device | Physics | 3 | Active |
| US7336518B2 | Layout for equalizer and data line sense amplifier employed in a high speed memory device | Physics | 2 | Expired |
| US9620197B1 | Circuit for driving sense amplifier of semiconductor memory device and operating method thereof | Physics | 2 | Active |
| US8189406B2 | Device and method generating internal voltage in semiconductor memory device | Physics | 1 | Active |
| US11961551B2 | Bitline sense amplifier and a memory device with an equalizer | Physics | 1 | Active |
| US7075849B2 | Semiconductor memory device and layout method thereof | Physics | 1 | Expired |
| US7352636B2 | Circuit and method for generating boosted voltage in semiconductor memory device | Physics | 0 | Expired |
| US11881283B2 | Semiconductor memory device and memory system including memory cell arrays and column selection transistors arranged to improve size efficiency | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.