Non-volatile memory cell, array and fabrication method
US10726894B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Dec 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a non-volatile memory cell, array and fabrication method. The memory cell comprises a substrate, a gate structure, a source region and a drain region, wherein the gate structure is formed on the substrate, the gate structure sequentially comprises a first gate dielectric layer, a first conductive layer, a second gate dielectric layer and a second conductive layer from bottom to top, the source region is formed in the substrate, the source region comprises an N-type heavily doped source region, the drain region is formed in the substrate, the drain region comprises an N-type doped drain region and a P-type heavily doped drain region formed in the N-type doped drain region. The non-volatile memory cell and array provided by the present invention have a band-to-band tunneling programming ability and reserve the advantage of high reading current of an N-channel at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.