Increased terrace configuration for non-volatile memory
US10726921B2 · kind B2 · utility
0Cited by
8References
17Claims
0Family size
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Key dates
| Filing date | Mar 30, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Mar 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0466
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional block includes a stack comprising a plurality of control gate layers configured to bias memory cells of the block. The block includes a plurality of track regions that includes three or more hookup regions. The plurality of track regions separate the memory cells into three memory cell regions. Tracks extending in the track regions supply voltages to the hookup regions. A system includes a memory plane of blocks, and a plurality of track regions, each extending across the memory plane of blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.