Method for creating through-connected vias and conductors on a substrate
US10727084B2 · kind B2 · utility
3Cited by
27References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2020 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49866
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor through the substrate, by forming structures in the planes of a substrate. These structures may include interconnect lines, bond pads, and other structures, and improve the performance of subsequent unique processing while simultaneously reducing the manufacturing complexity to reduce time and cost. These structures are formed by selective etching using chemical mechanical polishing, and then completed using a single fill step with a conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.