Chip packaging structure and packaging method
US10727196B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Nov 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip packaging structure comprises a die, a carrier, a die attach film, and a plastic package body. The die attach film is disposed on the bottom surface of the die, with a thickness of the die attach film being greater than or equal to 40 micrometers. The die is disposed on the carrier via the die attach film; and the plastic package body is disposed on the carrier and coats a top surface and side surfaces of the die, whereby the overall impact resistance of a chip is improved without changing the structure of the carrier, the expense for making a mold is saved, and moreover, the packaging structure is simple and easy for mass production.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.