Memory device including bump arrays spaced apart from each other and electronic device including the same
US10727200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Oct 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the first processor through the second channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.