Hybrid bonding technology for stacking integrated circuits
US10727205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2018 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Aug 15, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06565
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.