Layout of semiconductor transistor device

US10727234B2 · kind B2 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Zhibiao Zhou · Singapore, SG
• Ding-Lung Chen · Singapore, SG
• Xing Zhang · Beijing, CN
• Shan Liu · Central, US
• Runshun Wang · Singapore, SG
• Chien-Fu Chen · Banluliao, TW
• Wei Wang · Westborough, US
• Chen-Hsien Hsu · Dashulong, TW

Key dates

• Filing date: Nov 27, 2016
• Grant date: Jul 28, 2020
• Expiry date: Dec 19, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

The present invention provides a layout of a semiconductor transistor device including a first and a second active area, a first and a second gate, and a metal line. The first active and the second active area are extended along a first direction. The first gate and the second gate are extended along a second direction and crossed the first active area, to define two transistors. The two transistors are electrically connected with each other through a conductive layer. The metal line is disposed on the conductive layer and is electrically connected the two transistors respectively.