Three dimensional memory device fabricating method and applications thereof
US10727243B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | May 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A 3D memory device includes a multi-layers stacking structure having a plurality of conductive layers and insulating layers stacked in a staggered manner, at least one trench passing through the conductive layers and a plurality of recess regions extending into the conductive layers from the trench; a dielectric blocking strip lining sidewalls of the trench and the recess regions; a plurality of floating gates disposed in the recess regions and isolated from the conductive layers by the dielectric blocking strip; a dielectric strip overlies sidewalls of the floating gates exposed from the recess regions; a semiconductor strip disposed in the trench, insulated from the floating gates by the dielectric strip, and includes a first doping region, a second doping region and a channel region disposed between and connects to the first doping region and the second doping region, and overlapping with the floating gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.