Techniques for MRAM top electrode via connection

US10727274B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Sheng-Chang Chen · Hsinchu, TW
• Harry-Hak-Lay Chuang · Austin, US
• Hung Cho Wang · Taipei, TW
• Sheng-Huang Huang · Hsinchu, TW

Key dates

• Filing date: May 15, 2019
• Grant date: Jul 28, 2020
• Expiry date: May 15, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/80
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.