Lateral DMOS device with dummy gate

US10727334B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Chun-Wai Ng · Baoshan, TW
• Ruey-Hsin Liu · Baoshan, TW
• Jun Cai · Allen, US
• Hsueh-Liang Chou · Zhubei City, TW
• Chi-Chih Chen · Baoshan, TW

Key dates

• Filing date: Oct 1, 2019
• Grant date: Jul 28, 2020
• Expiry date: Oct 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/516

Abstract

An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.