Reference clock frequency change handling in a phase-locked loop
US10727844B1 · kind B1 · utility
6Cited by
22References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/235
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.