Use of a virtual clock in a PLL to maintain a closed loop system
US10727845B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2019 |
| Grant date | Jul 28, 2020 |
| Priority date | — |
| Expiry date | Jun 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A PLL uses a virtual clock signal during holdover and/or startup to maintain a closed loop for the PLL and allow for phase/frequency adjustment of the PLL output through the feedback divider during holdover/startup when reference clock(s) supplied to the PLL are unavailable. The virtual clock signal is a series of digital values separated by a time period, where the digital values indicate transitions of the virtual clock signal and the time period corresponds to a period of the virtual clock signal. A selector circuit selects as a digital reference clock signal the virtual clock signal in a holdover or startup mode and another reference clock signal in normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.