System and method employing three-dimensional (3D) emulation of in-kerf optical macros
US10733354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Jan 1, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are embodiments of a system, method and computer program product for wafer-level design including chip and frame design. The embodiments employ three-dimensional (3D) emulation to preliminarily verify in-kerf optical macros included in a frame design layout. Specifically, 3D images of a given in-kerf optical macro at different process steps are generated by a 3D emulator and a determination is made as to whether or not that macro will be formed as predicted. If not, the plan for the macro is altered using an iterative design process. Once the in-kerf optical macros within the frame design layout have been preliminarily verified, wafer-level design layout verification, including chip and frame design layout verification, is performed. Once the wafer-level design layout has been verified, wafer-level design layout validation, including chip and frame design layout validation, is performed. Optionally, an emulation library can store results of 3D emulation processes for future use.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.