Patent · US Active

Packaged integrated circuit having stacked die and method for therefor

US10734312B2 · kind B2 · utility

0Cited by

9References

20Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Burton J. Carpenter · Austin, US
Kim R. Gauen · Noblesville, US

Key dates

Filing date	Jul 18, 2018
Grant date	Aug 4, 2020
Priority date	—
Expiry date	Jul 18, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2224/94
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A packaged integrated circuit (IC) device includes a first set of stacked die having a first IC die, a first inductor in the first IC die, an isolation layer over the first IC die, a second IC die over the isolation layer, and a second inductor in the second IC die aligned to communicate with the first inductor, and a second set of stacked die having a third IC die, a third inductor in the third IC die, a second isolation layer over the third IC die, a fourth IC die over the second isolation layer, and a fourth inductor in the fourth IC die aligned to communicate with the third inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die, and the second isolation layer extends a second prespecified distance beyond a first edge of the fourth IC die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.