Power metallization structure for semiconductor devices

US10734320B2 · kind B2 · utility

Assignee

• Infineon Technologies Austria AG · AT

Inventors

• Ravi Keshav Joshi · Klagenfurt, AT
• Rainer Pelzer · Wernberg, AT
• Axel Buerke · Dresden, DE
• Sven Schmidbauer · Dresden, DE
• Michael Nelhiebel · Villach, AT

Key dates

• Filing date: Jul 30, 2018
• Grant date: Aug 4, 2020
• Expiry date: Jul 30, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/53223
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a semiconductor substrate, a power metallization structure formed above the semiconductor substrate and a barrier layer formed between the power metallization structure and the semiconductor substrate. The barrier layer is configured to prevent diffusion of metal atoms from the power metallization structure in a direction toward the semiconductor substrate. The power metallization structure is in direct contact with the barrier layer or an electrically conductive layer formed on the barrier layer in a first region. The semiconductor device further includes a passivation layer interposed between the barrier layer and the power metallization structure in a second region. Corresponding methods of manufacturing the semiconductor device are also described.