Three-dimensional memory devices and fabricating methods thereof
US10734397B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Aug 4, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/251
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a 3D memory device is disclosed. The method includes: forming an first insulating layer on a substrate in a peripheral region, the first insulating layer having a slope near a boundary between the peripheral region and a core region of the substrate; forming an alternating conductive/dielectric stack on the substrate and the slope of the first insulating layer, a lateral portion of the alternating conductive/dielectric stack extending along a top surface of the substrate in the core region, and an inclined portion of the alternating conductive/dielectric stack extending along the slope of the first insulating layer; and forming a plurality of contacts to electrically contact a plurality of conductive layers in the inclined portion of the alternating conductive/dielectric stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.