Backside contact resistance reduction for semiconductor devices with metallization on both sides

US10734412B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Anand S. Murthy · Beaverton, US
• Karthik Jambunathan · Hillsboro, US
• Chandra S. Mohapatra · Hillsboro, US
• Mauro J. Kobrinsky · Portland, US
• Patrick Morrow · Portland, US

Key dates

• Filing date: Jul 1, 2016
• Grant date: Aug 4, 2020
• Expiry date: Jul 1, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material. Other embodiments may be described and/or disclosed.