Inventor · Portland, OR, US

Patrick Morrow

187Patents
18h-index
134Co-inventors
89Inventor score

Filing activity: Nov 5, 1999 → Jan 22, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US7410884B2 3D integrated circuits using thick metal for backside connections and offset bumps Electricity 245 Active
US6946384B2 Stacked device underfill and a method of fabrication Electricity 219 Expired
US6887762B1 Method of fabricating a field effect transistor structure with abrupt source/drain junctions Electricity 103 Expired
US6797556B2 MOS transistor structure and method of fabrication Electricity 90 Expired
US6541343B1 Methods of making field effect transistor structure with partially isolated source/drain junctions Electricity 69 Expired
US7056813B2 Methods of forming backside connections on a wafer stack Electricity 62 Expired
US6897125B2 Methods of forming backside connections on a wafer stack Electricity 59 Expired
US7274191B2 Integrated on-chip NMR and ESR device and method for making and using the same Physics 52 Expired
US6479391B2 Method for making a dual damascene interconnect using a multilayer hard mask Electricity 48 Expired
US7345479B2 Portable NMR device and method for making and using the same Physics 47 Expired
US7391087B2 MOS transistor structure and method of fabrication Electricity 37 Expired
US6448177B1 Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure Electricity 33 Expired
US7129172B2 Bonded wafer processing method Emerging Cross-Sectional Technologies 31 Expired
US7436035B2 Method of fabricating a field effect transistor structure with abrupt source/drain junctions Electricity 29 Expired
US7682916B2 Field effect transistor structure with abrupt source/drain junctions Electricity 29 Active
US7338873B2 Method of fabricating a field effect transistor structure with abrupt source/drain junctions Electricity 24 Expired
US9685436B2 Monolithic three-dimensional (3D) ICs with local inter-level interconnects Electricity 21 Active
US7755124B2 Laminating magnetic materials in a semiconductor device Emerging Cross-Sectional Technologies 18 Active
US8421225B2 Three-dimensional stacked substrate arrangements Electricity 14 Active
US10872820B2 Integrated circuit structures Emerging Cross-Sectional Technologies 13 Active
US10068874B2 Method for direct integration of memory die to logic die without use of thru silicon vias (TSV) Electricity 11 Active
US10886217B2 Integrated circuit device with back-side interconnection to deep source/drain semiconductor Electricity 11 Active
US10734412B2 Backside contact resistance reduction for semiconductor devices with metallization on both sides Electricity 11 Active
US7214594B2 Method of making semiconductor device using a novel interconnect cladding layer Electricity 11 Expired
US6661094B2 Semiconductor device having a dual damascene interconnect spaced from a support structure Electricity 9 Expired

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.