Interface scheduler for a distributed memory system
US10740031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Sep 25, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An Address and Command chip of a distributed memory system includes a memory controller, a first communication link, and one or more interface schedulers, where the one or more interface schedulers include a first interface scheduler residing communicatively between the memory controller and the first communication link. The first interface scheduler is configured to receive a first communication directed from the memory controller to the first communication link; capture the first communication before the first command reaches the first communication link; postpone the first communication for a first set of one or more memory cycles; and reissue the first communication to the first communication link in association with a first cycle offset code indicating how many memory cycles the first command was postponed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.