Multi-core processor and cache management method thereof
US10740167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | May 29, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor connected to main memory or peripheral device and having dual modular redundancy mode in which each processor performs the same task includes a first processor which generates first write-in data by performing the task, and writes the first write-in data to the main memory or peripheral device after fault detection operation on the first write-in data, a second processor which generates second write-in data by performing the task, and prevents writing of the second write-in data to the main memory or peripheral device after the fault detection operation on the second write-in data, and a fault manager which performs the fault detection operation by comparing the first write-in data with the second write-in data in the mode, wherein the first write-in data is written to the main memory using first data cache, which is managed using dirty bit indicating whether to synchronize with the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.