Memory device, memory system, and operation method thereof
US10740226B2 · kind B2 · utility
1Cited by
1References
5Claims
0Family size
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Key dates
| Filing date | Oct 25, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is provided. The memory device includes a plurality of normal memory blocks; and at least two or more bad memory blocks, wherein data having the same number of bits as data to be stored in a normal memory block and a parity code having the number of bits at least twice greater than that of a parity code to be stored in the normal memory block are stored in a first bad memory block and a second bad memory block among the bad memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.