Patent · US Active

System, method and computer program product for accelerating iterative graph algorithms by memory layout optimization

US10740232B2 · kind B2 · utility

1Cited by

2References

20Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Minsik Cho · Austin, US
Daniel Brand · Cologne, DE
Ulrich A. Finkler · Mahopac, US
David S. Kung · Palo Alto, US
Ruchir Puri · Peekskill, US

Key dates

Filing date	Dec 12, 2018
Grant date	Aug 11, 2020
Priority date	—
Expiry date	Dec 12, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/60
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An iterative graph algorithm accelerating method, system, and computer program product, include recording an order of access nodes in a memory layout, reordering the access nodes in the memory layout in accordance with the recorded order, and updating edge information of the reordered access nodes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.