Semiconductor packages
US10741529B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Dec 31, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.