Semiconductor structure and manufacturing method thereof
US10741537B2 · kind B2 · utility
31Cited by
19References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Oct 5, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P80/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.