Mill-Jer Wang
79Patents
7h-index
65Co-inventors
71Inventor score
Filing activity: Jun 3, 2008 → Nov 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10741537B2 | Semiconductor structure and manufacturing method thereof | Emerging Cross-Sectional Technologies | 31 | Active |
| US9086452B2 | Three-dimensional integrated circuit and method for wireless information access thereof | Electricity | 25 | Active |
| US7750651B2 | Wafer level test probe card | Emerging Cross-Sectional Technologies | 11 | Active |
| US9341671B2 | Testing holders for chip unit and die package | Physics | 9 | Active |
| US8421073B2 | Test structures for through silicon vias (TSVs) of three dimensional integrated circuit (3DIC) | Electricity | 8 | Active |
| US8922230B2 | 3D IC testing apparatus | Emerging Cross-Sectional Technologies | 8 | Active |
| US8957691B2 | Probe cards for probing integrated circuits | Physics | 7 | Active |
| US9453877B2 | Testing holders for chip unit and die package | Physics | 6 | Active |
| US9664707B2 | Testing holders for chip unit and die package | Physics | 6 | Active |
| US9568543B2 | Structure and method for testing stacked CMOS structure | Electricity | 5 | Active |
| US10652987B2 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Electricity | 4 | Active |
| US8836363B2 | Probe card partition scheme | Physics | 4 | Active |
| US9817029B2 | Test probing structure | Electricity | 4 | Active |
| US9417285B2 | Integrated fan-out package-on-package testing | Electricity | 4 | Active |
| US9658281B2 | Alignment testing for tiered semiconductor structure | Physics | 4 | Active |
| US9671457B2 | 3D IC testing apparatus | Emerging Cross-Sectional Technologies | 4 | Active |
| US8956889B2 | Method of testing through silicon VIAS (TSVs) of three dimensional integrated circuit (3DIC) | Electricity | 3 | Active |
| US8866488B2 | Power compensation in 3DIC testing | Physics | 3 | Active |
| US9252593B2 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Electricity | 3 | Active |
| US8146245B2 | Method for assembling a wafer level test probe card | Emerging Cross-Sectional Technologies | 3 | Active |
| US9372227B2 | Integrated circuit test system and method | Physics | 3 | Active |
| US9754847B2 | Circuit probing structures and methods for probing the same | Electricity | 3 | Active |
| US10067181B2 | Testing holders for chip unit and die package | Physics | 3 | Active |
| US9900970B2 | Three dimensional integrated circuit electrostatic discharge protection and prevention test interface | Electricity | 2 | Active |
| US10073135B2 | Alignment testing for tiered semiconductor structure | Physics | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.