Transistors patterned with electrostatic discharge protection and methods of fabrication
US10741542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2018 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Nov 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/116
Abstract
High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.