Semiconductor device and manufacturing method thereof
US10741569B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Oct 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6892
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.