Encapsulation layer for vertical transport field-effect transistor gate stack
US10741663B1 · kind B1 · utility
3Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Apr 3, 2019 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Apr 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/405
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical transport field-effect transistor includes gate metal protected by a conformal encapsulation layer. Techniques for fabricating the transistor include depositing the conformal encapsulation layer over the gate metal prior to depositing an additional encapsulation layer such as a nitride layer. The conformal encapsulation layer protects the gate metal during deposition of the additional encapsulation layer, thereby avoiding oxidation or nitridation of the gate metal. The conformal encapsulation layer may be an amorphous silicon layer deposited at relatively low temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.