Buffer management for plug-in architectures in computation graph structures
US10742834B2 · kind B2 · utility
2Cited by
1References
13Claims
0Family size
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Key dates
| Filing date | Jul 28, 2017 |
| Grant date | Aug 11, 2020 |
| Priority date | — |
| Expiry date | Aug 20, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/0087
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer vision processing device is provided which comprises memory configured to store data and a processor. The processor is configured to store captured image data in a first buffer and acquire access to the captured image data in the first buffer when the captured image data is available for processing. The processor is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data when a last operation of the first group of operations executes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.