Method and apparatus for at-speed scan shift frequency test optimization
US10746795B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2012 |
| Grant date | Aug 18, 2020 |
| Priority date | — |
| Expiry date | Apr 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2851
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.